Among various semiconductor memory devices, a DRAM is one of the semiconductor memory devices most suitable for a large density, and is widely used for a main memory and the like of a computer. A prime reason that the DRAM is excellent for a large density is that a memory configuration of the DRAM is remarkably simple as compared with those of other semiconductor memory devices. In other words, each of memory cells of the DRAM includes one capacitor and one MOS transistor, and stores information based on a charge amount stored in the capacitor. Charging to and discharging from the capacitor are controlled by the MOS transistor connected to word lines. When the MOS transistor is turned on, a storage node of the capacitor is connected to a corresponding bit line, thereby making it possible to read or write the information.
Because the memory cells of the DRAM store information based on the charge amount stored in the capacitor as described above, the stored information is disappeared by a leak current, unless a refresh operation is executed periodically. Therefore, all memory cells need to be refreshed before the information disappears due to the leak current. A refresh cycle tREF of refreshing all memory cells is prescribed as 64 milliseconds, for example, by a standard. This means that time equal to or larger than tREF is required as information holding time of each memory cell. Accordingly, a memory cell of which information holding time is shorter than tREF is a “refresh defective cell”, and the address corresponding to the refresh defective cell is treated as a “refresh defective address”. Usually, the refresh defective address is relieved by replacing the refresh defective cell with a redundant memory cell, and the cell is shipped as a normal chip.
However, along with the progress of miniaturization and a capacity increase, the number of refresh defective cells contained in one chip becomes very large. Therefore, in recent years, the number of redundant memory cells to be prepared for one chip and the number of fuse elements (ROM) to store defective addresses have become very large, and this interrupts the capacity increase.
In order to solve these problems, instead of replacing all refresh defective cells with redundant memory cells, it is considered suitable to relieve the refresh defective addresses by increasing the execution frequency of the refresh operation for the refresh defective cells of which information holding time is slightly shorter than tREF. For example, for the refresh defective cells having information holding time shorter than tREF (for example, 64 msec) and equal to or longer than tREF/2 (for example, 32 msec), the refresh defective addresses can be relieved by increasing the execution frequency of the refresh operation to two times, without replacing the refresh defective cells with the redundant memory cells (refresh-relief).
A technique of relieving the refresh defective cells by increasing the execution frequency of the refresh operation of only specific cells is described in Japanese Patent Application Laid-open Nos. 2000-132963 and 2005-116106. According to this (multiple refresh) technique, when an address of which only a part of bits is different from bits of the refresh defective address is given from the refresh counter, word lines corresponding to the refresh defective cells as well as word lines corresponding to the address indicated by the refresh counter are simultaneously activated.
As refresh modes of a DRAM, there are an auto-refresh mode and a self-refresh mode. The former is a mode for executing refresh in response to an external refresh command supplied from the outside. By inserting the auto-refresh mode into between a read operation and a write operation, all memory cells are controlled to be refreshed during the tREF period. On the other hand, the latter is a mode for executing refresh in response to an internal refresh command that is automatically generated in the inside. The self-refresh mode is executed when the DRAM is in a power down state.
Because the auto-refresh is executed during a period while the normal read operation or the write operation is being executed, power consumption of the refresh operation has little problem in the specification. However, a power source voltage easily changes by the execution of the read operation or the write operation. Further, a chip temperature rises due to heat generation by the read operation or the write operation, and there is a possibility that an information holding characteristic of memory cells decreases during the auto-refresh time.
On the other hand, during the self-refresh time, the DRAM is in a power down state, and there is little change in the power source voltage. Because the chip temperature is also stabilized, the information holding characteristic of the memory cells is in a high state. However, because the power consumption permitted in the power down state is very small in the specification, executing a multiple refresh over a wide range has a risk of not satisfying the current standard.
As explained above, when the multiple refresh is executed, the refresh defective cells can be relieved without replacing the refresh defective cells with the redundant memory cells. However when the multiple refresh is performed, power consumption during the self-refresh time becomes the problem.
As a technique of decreasing power consumption during the self-refresh, a method of not carrying out refresh to a part of memory cells during the self-refresh time is proposed as described in Japanese Patent Application Laid-open Nos. 2002-157880, 2000-298982, and 2003-68075. A method of decreasing the power consumption during the self-refresh time by adjusting the cycle of the refresh timer according to the chip temperature is described in Japanese Patent Application Laid-open Nos. 2002-117671 and 2006-172526.
However, the methods described in Japanese Patent Application Laid-open Nos. 2002-157880, 2000-298982, and 2003-68075 are based on the assumption that a part of data is destroyed. Therefore, it is considered that these methods cannot be applied in substantially all cases. The methods described in Japanese Patent Application Laid-open Nos. 2002-117671 and 2006-172526 can decrease power consumption according to a chip temperature. However, the increase in the power consumption due to the multiple refresh cannot be suppressed.